In any digital communications system there are transmitters and receivers that are physically separated and communicate over a medium such as a wire or air. The digital communication systems may transmit data such as a Quadrature Amplitude Modulated (QAM) or Quadrature Phase Shift Keying (QPSK) signals that represent a bitstream, which includes a series of symbols formed from a number of bits. To recover the data, the receiver will convert the analog signal received into a digital signal and will distinguish the symbols in the bitstream. In properly handling the incoming signal, the timing of sampling (or symbol timing) should be properly addressed.
A receiver will typically have a reference clock for timing that is only nominally at the same frequency and phase as the transmitter clock. In order to receive the data correctly, the data should be sampled at or near the same rate as the transmitter clock. To this end, the receiver must synchronize its clock with that of the transmitter. This is called "timing recovery." The larger the number of bits per hertz of bandwidth being transmitted, the higher is the system signal-to-noise ratio (SNR) requirement and the more accurate the timing recovery requirements. There are a number of techniques that may be used for timing recovery.
One timing-recovery approach is to use a mixed analog/digital loop. In this approach, an oversampled analog-to-digital converter (ADC) samples the incoming analog signal and communicates it to a digital signal processor (DSP). The digital signal processor may process the digital signal with a timing recovery algorithm to generate an adjustment signal. The adjustment signal is provided to a digital-to-analog converter (DAC), which provides an appropriate analog signal to a voltage-controlled oscillator (VCO) to adjust the timing or clock signal for the ADC. The performance of the DAC/VCO approach depends largely on the accuracy of the VCO which can degrade over time. The mixed analog/digital feedback may also be inconvenient. See generally, U.S. Pat. No. 5,388,127, entitled "Timing Recovery Circuit," which is incorporated herein by reference for all purposes.
Numerous time recovery algorithms are known in the art for use as a timing recovery algorithm in such a design. See, Floyd M. Gardner, "Phaselock Techniques," (1979). For example, a technique know as band-edge component maximization (BECM) may used. The BECM approach is described in Dominique N. Godard, "Passband Timing Recovery In An All-Digital Modem Receiver," IEEE Trans. Communications, Vol. Com-26, No. 5, May 1978, pp. 517-523. The timing extraction taught in the Godard article allows quick sampling phase acquisition and is readily implemented with a DSP.
Another approach to timing recovery has involved implementing interpolating filters in an all-digital timing recovery system. In this approach, the signal is sampled by an ADC at a constant rate and then digitally interpolated with a filter. The resultant digital signal may be processed with a time recovery algorithm in a DSP much as before, but the timing adjustment is made at the interpolation filter, rather than at the oscillator. This approach may eliminate potential errors due to drift and initial inaccuracies in the oscillator. Because the signal from the ADC is bandlimited and has been sampled above the nyquist rate, accurate interpolation of the value of any point located between two sampled points is possible, i.e., in essence this method reconstructs the continuous bandlimited signal and resamples it.
The interpolator is a filter. It can be a number of different filter types or combinations of filters, but typically its sin (x/x) ("sinc") filter. The filter will approximate the values between actual samples, and the complexity of the filter will vary directly with the desired accuracy. The more accuracy desired, the more taps required. Usually the interpolation will involve numerous multiplies. A large interpolation filter may be required, and if so, may consume considerable power, increase the complexity of the circuit, and require many millions of instructions per second (MIPS) be processed.
Though accurate resampling with the interpolator approach is possible, it typically requires a significant amount of filtering, which poses its own drawbacks such as adding considerable complexity to the circuit. In this regard, a number of the approaches to interpolation are known in the art and many are taught in a recent article. Timo I. Laakso, Vesa Valimaki, Matti Karjalainen, and Unto K. Laine, Splitting The Unit Delay, IEEE Signal Processing, pp. 30-60, January 1996.
An approach that may be used with ADC-interpolation-filter approach is Farrow's method, which is summarized in the above-noted article. This approach involves a set of filters approximating a fractional delay, d, in the desired range and approximating each coefficient as a Pth-order polynomial of d: ##EQU1## wherein c.sub.m (n) are real-valued approximating coefficients. Each coefficient is a function of the fractional delay, d. The transfer function of the filter can be detailed into the following: ##EQU2## where ##EQU3##
This presentation indicates the implementation of Farrow's method with parallel fixed filters with output taps weighted by an appropriate power of d.